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? semiconductor components industries, llc, 2011 may, 2011 ? rev. 25 1 publication order number: ncv8184/d ncv8184 micropower 70 ma low dropout tracking regulator/line driver the ncv8184 is a monolithic integrated low dropout tracking voltage regulator designed to provide an adjustable buffered output voltage that closely tracks ( 3.0 mv) the reference input. the part can be used in automotive applications with remote sensors, or any situation where it is necessary to isolate the output of your regulator. the ncv8184 also enables the user to bestow a quick upgrade to their module when added current is needed, and the existing regulator cannot provide. the versatility of this part also en ables it to be used as a high ? side driver. features ? 70 ma source capability ? output tracks within 3 .0 mv ? low input voltage tracking performance (works down to v ref = 2.1 v) ? low dropout (0.35 v typ. @ 50 ma) ? low quiescent current ? thermal shutdown ? wide operating range ? internally fused leads in soic ? 8 package ? ncv prefix, for automotive and other applications requiring site and change control ? aec qualified ? ppap capable ? these are pb ? free devices figure 1. block diagram ? + bias thermal shutdown current limit & saturation sense v in adj v ref /enable v out gnd soic ? 8 d suffix case 751 1 dpak 5 ? lead dt suffix case 175aa v ref /enable adj gnd gnd gnd gnd v in v out pin connections and marking diagrams 8184g alyww 1 pin 1. v in 2. v out tab, 3. gnd 4. adj 5. v ref /enable 1 http://onsemi.com 8184 = device code a = assembly location l = wafer lot y = year w, ww = work week or g = pb ? free package 8184 alyw 1 1 8 soic ? 8 ep p suffix case 751ac see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information 1 8 8184 ayww v ref /enable adj nc gnd nc nc v in v out
ncv8184 http://onsemi.com 2 maximum ratings rating value unit storage temperature ? 65 to 150 c supply voltage range (continuous) ? 15 to 45 v supply voltage operating range 4.0 to 42 v peak transient voltage (v in = 14 v, load dump transient = 31 v) 45 v voltage range (v out , adj) ? 3.0 to 45 v voltage range (v ref /enable) ? 0.3 to 45 v maximum junction temperature 150 c esd capability human body model machine model charge device model 2.5 200 1000 kv v v lead temperature soldering: reflow: (smd styles only) (note 1) 240 peak 260 peak (pb ? free) (note 2) c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. 2. ? 5 c / +0 c allowable conditions, applies to both pb and pb ? free devices. thermal characteristics see package thermal data section (page 8) electrical characteristics (v in = 14 v; v ref /enable > 2.1 v; ? 40 c < t j < +150 c; c out = 1.0 f; i out = 1.0 ma; adj = v out ; c out ? esr = 1.0 , unless otherwise specified.) parameter test conditions min typ max unit regulator output v ref /enable ? v out v out tracking error 5.7 v v in 26 v, 100 a i out 60 ma 2.1 v v ref /enable (v in ? 600 mv) ? 3.0 ? 3.0 mv dropout voltage (v in ? v out ) i out = 100 a i out = 5.0 ma i out = 60 ma ? ? ? 100 250 350 150 500 600 mv mv mv line regulation 5.7 v v in 26 v, v ref /enable = 5.0 v ? ? 3.0 mv load regulation 100 a i out 60 ma, v ref /enable = 5.0 v ? ? 3.0 mv adj input bias current v ref /enable = 5.0 v ? 0.2 6.0 a current limit v in = 14 v, v ref = 5.0 v, v out = 90% of v ref (note 3) 70 ? 225 ma quiescent current (i in ? i out ) v in = 12 v, i out = 60 ma v in = 12 v, i out = 100 a v in = 12 v, v ref /enable = 0 v ? ? ? 5.0 50 ? 7.0 70 20 ma a a ripple rejection f = 120 hz, i out = 60 ma, 6.0 v v in 26 v 60 ? ? db thermal shutdown guaranteed by design 150 180 210 c v ref /enable enable voltage ? 0.8 ? 2.1 v input bias current v ref /enable = 5.0 v ? 0.2 3.0 a 3. v out connected to adj lead. package pin description package lead number lead symbol function soic ? 8 epad soic ? 8 dpak, 5 ? lead 8 8 1 v in battery supply input voltage. 1 1 2 v out regulated output. 3, epad 2, 3, 6, 7 tab, 3 gnd ground. 4 4 4 adj adjust lead, noninverting input. 5 5 5 v ref /enable reference voltage and enable input. 2, 6, 7 ? ? nc no connection. pcb traces allowed.
ncv8184 http://onsemi.com 3 typical performance characteristics ? 40 tracking error (mv) ? 0.3 temperature ( c) ? 0.1 0.2 0.4 ? 20 120 0 20 40 60 80 100 figure 2. tracking error vs. temperature tracking error (mv) ? 0.6 output current (ma) 0.4 0.6 1.0 0 20 30 50 40 60 70 0.8 ? 0.2 0.0 0.2 ? 0.4 figure 3. tracking error vs. output current figure 4. output stability with capacitor change figure 5. output stability with 0.1 f at low esr 0 esr ( ) 0 output current (ma) 5 10 15 20 25 50 10 20 30 40 70 unstable region 0 quiescent current (ma) 0 output current (ma) 2 4 6 8 10 12 10 20 30 40 50 60 70 0 quiescent current (ma) 0 input voltage (v) 0.5 1 1.5 2 2.5 510 25 15 20 i out = 1 ma i out = 20 ma figure 6. quiescent current vs. output current figure 7. quiescent current vs. input voltage ? 0.2 0.0 0.3 0.1 +25 c ? 40 c +125 c 10 60 50 30 35 40 45 stable region v out = 5.0 v v ref / enable = 5.0 v +25 c ? 40 c +125 c 0 esr ( ) 0.0 output current (ma) 0.5 1.0 1.5 2.0 2.5 10 20 30 40 70 unstable region 60 50 3.0 3.5 4.0 stable region c2 = 0.1 f v out = 5.0 v c2 = 10 f c2 = 0.1 f data is for 0.1 f only. capacitor values 0.5 f and above do not exhibit instability with low esr. i out = 50 ma
ncv8184 http://onsemi.com 4 typical performance characteristics +25 c ? 40 c +125 c 0 output voltage v out (v) 0 input voltage v in (v) 2 3 4 5 6 5101520 1 30 figure 8. dropout voltage vs. output current output voltage (v) 0 1 2 3 4 5 7 6 reference voltage (v) 01 figure 9. output voltage vs. input voltage figure 10. output voltage vs. reference voltage 234567 reference current ( a) 0.0 0.1 0.2 0.3 0.4 0.5 0.7 0.6 reference voltage (v) 012 34 5 67 25 0 thermal resistance, junction to ambient, r ja , ( c/w) copper area (in 2 ) 80 85 90 95 120 1234 6 5 100 105 110 115 figure 11. reference current vs. reference voltage figure 12. soic ? 8, ja as a function of the pad copper area (2.0 oz. cu thickness), board material = 0.0625 g ? 10/r ? 4 dropout voltage (v) 0.0 output current (ma) 0.5 0 20 30 50 40 60 70 0.2 0.3 0.4 0.1 10 +25 c ? 40 c +125 c v ref /enable = 5.0 v
ncv8184 http://onsemi.com 5 circuit description enable function by pulling the v ref /enable lead below 0.8 v, (see figure 16 or figure 17), the ic is disabled and enters a sleep state where the device draws less than 20 a from supply. when the v ref /enable lead is greater than 2.1 v, v out tracks the v ref /enable lead normally. output voltage the output is capable of supplying 70 ma to the load while c onfigured as a similar (f igure 13), lower (figure 15), or higher (figure 14) voltage as the reference lead. the adj lead acts as the inverting terminal of the op amp and the v ref lead as the non ? inverting. the device can also be configured as a high ? side driver as displayed in figure 18. figure 13. tracking regulator at the same voltage figure 14. tracking regulator at higher voltages v in v out gnd gnd v ref / gnd gnd adj enable loads 5.0 v b+ c1* 1.0 f c2** 10 f v out , 70 ma v out v ref v in v out gnd gnd v ref / gnd gnd adj enable loads v re f b+ c1* 1.0 f c2** 10 f v out , 70 ma r a r f v out v ref (1 r e r a ) ncv8184 ncv8184 c3*** 10 nf c3*** 10 nf figure 15. tracking regulator at lower voltages figure 16. tracking regulator with enable circuit v in v out gnd gnd v ref / gnd gnd adj enable loads v ref b+ c1* 1.0 f c2** 10 f v out , 70 ma v out v ref ( r2 r1 r2 ) r2 r1 v in v out gnd gnd v ref / gnd gnd adj enable from mcu v re f b+ c1* 1.0 f c2** 10 f v out , 70 ma r ncv8184 ncv8184 c3*** 10 nf c3*** 10 nf figure 17. alternative enable circuit figure 18. high ? side driver v in v out gnd gnd v ref / gnd gnd adj enable 10 f v in v out gnd gnd v ref / gnd gnd adj enable mcu b+ 70 ma v out b v sat ** c2 is required for stability. * c1 is required if the regulator is far from the power source filter. ncv8184 ncv8184 70 ma i/o ncv8501 6.0 v ? 40 v v in 100 nf v ref (5.0 v) c to load (e.g. sensor) c1* 1.0 f c3*** 10 nf c3*** 10 nf *** c3 is recommended for emc susceptibility
ncv8184 http://onsemi.com 6 application notes v out short to battery the ncv8184 will survive a short to battery when hooked up the conventional way as shown in figure 19. no damage to the part will occur. the part also endures a short to battery when powered by an isolated supply at a lower voltage as in figure 20. in this case the ncv8184 supply input voltage is set at 7.0 v when a short to battery (14 v typical) occurs on v out which normally runs at 5.0 v. the current into the device (ammeter in figure 20) will draw additional current as displayed in figure 21. v out gnd gnd adj v in gnd gnd v ref / enable v out 5.0 v 70 ma c1* 1.0 f automotive battery typically 14 v short to battery ncv8184 figure 19. c2** 10 f v out gnd gnd adj v in gnd gnd v ref / enable v out c1* 1.0 f ncv8184 figure 20. c2** 10 f c3*** 10 nf v out = v ref 5.0 v loads b+ 5.0 v 70 ma automotive battery typically 14 v short to battery v out = v ref 5.0 v loads b+ c3*** 10 nf a 7 v ** c2 is required for stability. * c1 is required if the regulator is far from the power source filter. *** c3 is recommended for emc susceptibility. + ? + ? + ? + ? figure 21. v out short to battery 18 16 14 12 10 6 4 2 0 6 510152025 v out voltage (v) current (ma) 8 7 8 9 11121314 16171819 21222324 26 switched application the ncv8184 has been designed for use in systems where the reference voltage on the v ref /enable pin is continuously on. typically, the current into the v ref /enable pin will be less than 1.0 a when the voltage on the v in pin (usually the ignition line) has been switched out (v in can be at high impedance or at ground.) reference figure 22. v out gnd gnd adj v in gnd gnd v ref / enable v out v ref 5.0 v v bat c1 1.0 f ignition switch < 1.0 a ncv8184 figure 22. c2 10 f
ncv8184 http://onsemi.com 7 external capacitors the output capacitor for the ncv8184 is required for stability. without it, the regulator output will oscillate. actual size and type may vary depending upon the application load and temperature range. capacitor ef fective series resistance (esr) is also a factor in the ic stability. worst ? case is determined at the minimum ambient temperature and maximum load expected. the output capacitor can be increased in size to any desired va lue above the minimum. one possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. the capacitor must also be rated at all ambient temperatures expected in the system. to maintain regulator stability down to ? 40 c, a capacitor rated at that temperature must be used. more information on capacitor selection for smart regulator ? s is available in the smart regulator application note, ?compensation for linear regulators,? document number sr003an/d, available through our website at http://www.onsemi.com. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 23) is: pd(max) { v in (max) v out (min) } i out (max) v in (max)i q (eq. 1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current, for the application,and i q is the quiescent current the regulator consumes at i out(max) . once the value of pd(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (eq. 2) the value of r ja can then be compared with those in the package thermal data section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heat sink will be required. figure 23. single output regulator with key performance parameters labeled i in i out i q smart v out v in regulator ? control features heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja: r ja r jc r cs r sa (eq. 3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heatsink manufacturers.
ncv8184 http://onsemi.com 8 package thermal data parameter conditions typical value units soic ? 8 package 100 mm 2 spreader board 645 mm 2 spreader board 1 oz 2 oz 1 oz 2 oz junction ? to ? pin 6 ( ? jl6, jl6 ) 53 51 50 47 c/w junction ? to ? ambient (r ja , ja ) 151 135 111 100 c/w figure 24. pcb layout and package construction for simulation package construction without mold compound
ncv8184 http://onsemi.com 9 table 1. soic ? 8 thermal rc network models* copper area (1 oz thick) 100 mm 2 645 mm 2 100 mm 2 645 mm 2 cauer network foster network 100 mm 2 645 mm 2 units tau tau units c_c1 junction gnd 0.0000015 0.0000015 w ? s/c 1.00e-06 1.00e-06 sec c_c2 node1 gnd 0.0000059 0.0000059 w ? s/c 1.00e-05 1.00e-05 sec c_c3 node2 gnd 0.0000171 0.0000171 w ? s/c 1.00e-04 1.00e-04 sec c_c4 node3 gnd 0.0001340 0.0001340 w ? s/c 1.76e-04 1.76e-04 sec c_c5 node4 gnd 0.0001322 0.0001323 w ? s/c 0.0010 0.0010 sec c_c6 node5 gnd 0.0010797 0.0010811 w ? s/c 0.008 0.008 sec c_c7 node6 gnd 0.0087127 0.0087918 w ? s/c 0.150 0.150 sec c_c8 node7 gnd 0.0863882 0.0950421 w ? s/c 3.00 3.00 sec c_c9 node8 gnd 0.3109255 1.0127094 w ? s/c 8.96 5.15 sec c_c10 node9 gnd 0.8359004 1.5167041 w ? s/c 52.5 68.4 sec 100 mm 2 645 mm 2 r?s r?s r_r1 junction node1 0.8380955 0.8380935 c/w 0.49519 0.49519 c/w r_r2 node1 node2 1.9719907 1.9719679 c/w 1.070738 1.070738 c/w r_r3 node2 node3 5.0213740 5.0211819 c/w 3.385971 3.385971 c/w r_r4 node3 node4 3.1295806 3.1288061 c/w 1.617537 1.617537 c/w r_r5 node4 node5 3.2483544 3.2468794 c/w 5.10 5.10 c/w r_r6 node5 node6 6.5922506 6.5781209 c/w 7.00 7.00 c/w r_r7 node6 node7 16.5499898 16.2818051 c/w 15.00 15.00 c/w r_r8 node7 node8 45.3838437 34.7292748 c/w 20.00 20.00 c/w r_r9 node8 node9 32.8928798 7.6862725 c/w 28.19863 16.67727 c/w r_r10 node9 gnd 37.5059686 24.4060143 c/w 71.26626 33.54171 c/w *bold face items in the tables above represent the package without the external thermal system. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1 ? e ? t tau i
ncv8184 http://onsemi.com 10 80 90 100 110 120 130 140 150 160 0 100 200 300 400 500 600 700 1.0 oz cu 2.0 oz cu figure 25. soic ? 8, ja as a function of the pad copper area, board material fr4 ja ( c/w) copper heat spreader area (mm 2 ) 0.1 1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) figure 26. soic ? 8 thermal duty cycle curves on 1.0 in spreader test board, 1.0 oz cu (1.0 in pad pcb) die size = 2.08 x 1.55 x 0.40 5.0% active area duty cycle, d = t 1 t 2 p dm notes: t 1 t 2 50% duty cycle 20% single pulse 10% 5% 2% 1% r(t) ( c/w) 0.1 1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) figure 27. soic ? 8 single pulse heating curve cu area 645 mm 2 cu area 100 mm 2 r(t) ( c/w)
ncv8184 http://onsemi.com 11 package thermal data parameter conditions typical value units soic ? 8 ep package 100 mm 2 spreader board 645 mm 2 spreader board 1 oz 2 oz 1 oz 2 oz junction ? to ? board ( ? jb, jb ) 26 26 26 25 c/w junction ? to ? pin 6 (tab) ( ? jl6, jl6 ) 48 45 37 34 c/w junction ? to ? ambient (r ja , ja ) 140 123 88 78 c/w figure 28. pcb layout and package construction for simulation package construction without mold compound
ncv8184 http://onsemi.com 12 table 2. soic ? 8 ep thermal rc network models* drain copper area (1 oz thick) 100 mm 2 645 mm 2 100 mm 2 645 mm 2 (spice deck format) cauer network foster network 100 mm 2 645 mm 2 units tau tau units c_c1 junction gnd 0.0000015 0.0000015 w ? s/c 1.00e-06 1.00e-06 sec c_c2 node1 gnd 0.0000059 0.0000059 w ? s/c 1.00e-05 1.00e-05 sec c_c3 node2 gnd 0.0000171 0.0000172 w ? s/c 1.00e-04 1.00e-04 sec c_c4 node3 gnd 0.0001359 0.0001360 w ? s/c 1.76e-04 1.76e-04 sec c_c5 node4 gnd 0.0001349 0.0001352 w ? s/c 0.0010 0.0010 sec c_c6 node5 gnd 0.0011157 0.0011253 w ? s/c 0.008 0.008 sec c_c7 node6 gnd 0.0110409 0.0118562 w ? s/c 0.150 0.150 sec c_c8 node7 gnd 0.0963225 0.2080891 w ? s/c 3.00 3.00 sec c_c9 node8 gnd 0.3406538 1.1005982 w ? s/c 9.11 5.12 sec c_c10 node9 gnd 0.9202956 0.8512155 w ? s/c 52.1 68.6 sec 100 mm 2 645 mm 2 r?s r?s r_r1 junction node1 0.8378620 0.8378491 c/w 0.49519 0.49519 c/w r_r2 node1 node2 1.9693564 1.9692100 c/w 1.070738 1.070738 c/w r_r3 node2 node3 5.0005397 4.9993083 c/w 3.385971 3.385971 c/w r_r4 node3 node4 3.0695514 3.0646169 c/w 1.617537 1.617537 c/w r_r5 node4 node5 3.1989711 3.1895109 c/w 5.030483 5.030483 c/w r_r6 node5 node6 6.2274239 6.1397875 c/w 7.00 7.00 c/w r_r7 node6 node7 13.5796441 11.9712961 c/w 12.00 12.00 c/w r_r8 node7 node8 40.4842477 18.5111622 c/w 17.676107 7.880592 c/w r_r9 node8 node9 30.5112160 10.0330297 c/w 25.169021 8.550583 c/w r_r10 node9 gnd 33.6034987 27.3017101 c/w 65.037264 40.98639 c/w *bold face items in the tables above represent the package without the external thermal system. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1 ? e ? t tau i
ncv8184 http://onsemi.com 13 60 70 80 90 100 110 120 130 140 150 0 100 200 300 400 500 600 700 1.0 oz cu 2.0 oz cu figure 29. soic?8 exposed pad, ja as a function of the pad copper area, board material fr4 ja ( c/w) t j = 25 c copper heat spreader area (mm 2 ) 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) figure 30. soic?8 exposed pad thermal duty cycle curves on 1.0 in spreader test board, 1.0 oz cu 50% duty cycle 20% single pulse 10% 5% 2% 1% (1.0 in pad pcb) die size = 2.08 x 1.55 x 0.40 5.0% active area duty cycle, d = t 1 t 2 p dm notes: t 1 t 2 r(t) ( c/w) 0.1 1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) figure 31. soic?8 exposed pad single pulse heating curve cu area 645 mm 2 cu area 100 mm 2 r(t) ( c/w)
ncv8184 http://onsemi.com 14 package thermal data parameter conditions typical value units soic ? 8 ep package 100 mm 2 spreader board 645 mm 2 spreader board 1 oz 2 oz 1 oz 2 oz junction ? to ? board-top ( ? jb, jb ) 18 18 17 16 c/w junction ? to ? pin 3 (tab) ( ? jl3, jl3 ) 16 16 16 16 c/w junction ? to ? ambient (r ja , ja ) 87 77 62 55 c/w package construction without mold compound figure 32. pcb layout and package construction for simulation
ncv8184 http://onsemi.com 15 table 3. dpak 5 ? lead thermal rc network models* drain copper area (1 oz thick) 100 mm 2 645 mm 2 100 mm 2 645 mm 2 (spice deck format) cauer network foster network 100 mm 2 645 mm 2 units tau tau units c_c1 junction gnd 0.0000016 0.0000016 w ? s/c 1.00e-06 1.00e-06 sec c_c2 node1 gnd 0.0000060 0.0000060 w ? s/c 1.00e-05 1.00e-05 sec c_c3 node2 gnd 0.0000177 0.0000177 w ? s/c 1.00e-04 1.00e-04 sec c_c4 node3 gnd 0.0001586 0.0001587 w ? s/c 1.76e-04 1.76e-04 sec c_c5 node4 gnd 0.0001927 0.0001931 w ? s/c 0.0010 0.0010 sec c_c6 node5 gnd 0.0056684 0.0058019 w ? s/c 0.030 0.030 sec c_c7 node6 gnd 0.0832719 0.1225791 w ? s/c 0.285 0.299 sec c_c8 node7 gnd 0.1125429 0.3555671 w ? s/c 3.00 3.00 sec c_c9 node8 gnd 0.5161495 1.2959188 w ? s/c 9.03 11.80 sec c_c10 node9 gnd 1.4600223 1.8396650 w ? s/c 55.2 79.0 sec 100 mm 2 645 mm 2 r?s r?s r_r1 junction node1 0.8287213 0.8287120 c/w 0.490938 0.490938 c/w r_r2 node1 node2 1.9304163 1.9303119 c/w 1.061544 1.061544 c/w r_r3 node2 node3 4.7751915 4.7743247 c/w 3.356895 3.356895 c/w r_r4 node3 node4 2.3736457 2.3705112 c/w 1.606314 1.606314 c/w r_r5 node4 node5 2.0679537 2.0623650 c/w 5.00 5.00 c/w r_r6 node5 node6 5.3364094 5.1102633 c/w 5.00 5.00 c/w r_r7 node6 node7 6.0331860 3.2428679 c/w 2.00 2.00 c/w r_r8 node7 node8 22.7616126 8.6995800 c/w 9.147005 5.071663 c/w r_r9 node8 node9 17.9894079 16.1165074 c/w 17.23178 3.646957 c/w r_r10 node9 gnd 22.7199543 16.7871407 c/w 41.92202 34.68827 c/w *bold face items in the tables above represent the package without the external thermal system. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1 ? e ? t tau i
ncv8184 http://onsemi.com 16 40 45 50 55 60 65 70 75 80 85 90 0 100 200 300 400 500 600 700 figure 33. dpak 5 ? lead, ja as a function of the pad copper area, board material fr4 ja ( c/w) copper heat spreader area (mm 2 ) 1.0 oz cu 2.0 oz cu t j = 25 c 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 34. dpak 5 ? lead thermal duty cycle curves on 1.0 in spreader test board, 1.0 oz cu pulse time (sec) 50% duty cycle 20% single pulse 10% 5% 2% 1% (1.0 in pad pcb) die size = 2.08 x 1.55 x 0.40 5.0% active area duty cycle, d = t 1 t 2 p dm notes: t 1 t 2 r(t) ( c/w) 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) figure 35. dpak 5 ? lead single pulse heating curve cu area 645 mm 2 cu area 100 mm 2 r(t) ( c/w)
ncv8184 http://onsemi.com 17 junction ambient (thermal ground) r 1 r 2 c 1 c 2 c 3 c n r n r 3 time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. figure 36. grounded capacitor thermal network (?cauer? ladder) figure 37. non ? grounded capacitor thermal ladder (?foster? ladder) junction ambient (thermal ground) r 1 r 2 c 1 c 2 c 3 c n r n r 3 each rung is exactly characterized by its rc ? product time constant; amplitudes are the resistances ordering information device order number package type shipping ? ncv8184dg soic ? 8 (pb ? free) 98 units / tube ncv8184dr2g soic ? 8 (pb ? free) 2500 / tape & reel ncv8184dtrkg dpak (pb ? free) 2500 / tape & reel NCV8184PDG soic ? 8 epad (pb ? free) 98 units / tube ncv8184pdr2g soic ? 8 epad (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8184 http://onsemi.com 18 package dimensions soic ? 8 nb case 751 ? 07 issue aj 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m
ncv8184 http://onsemi.com 19 package dimensions ? 8 ep case 751ac ? 01 issue b ?? ?? h c 0.10 d e1 a d pin one 2 x 8 x seating plane exposed gauge plane 14 5 8 d c 0.10 a-b 2 x e b e c 0.10 2 x top view side view bottom view detail a end view section a ? a 8 x b a-b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 0 8 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc a1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* location exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 7.0 0.275 2.72 0.107
ncv8184 http://onsemi.com 20 package dimensions d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 12 34 5 dpak 5, center lead crop case 175aa ? 01 issue a 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8184/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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